1. Field of the Invention
The present invention generally relates to semiconductor processing technologies and, more specifically, to methods for etching a bottom anti-reflective coating (BARC) layer in a dual damascene etching process.
2. Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit density. The demands for greater circuit density necessitate a reduction in the dimensions of the integrated circuit components.
As the dimensions of the integrated circuit components are reduced (e.g. sub-micron dimensions), the materials used to fabricate such components contribute to their electrical performance. For example, metal interconnects with low resistance (e.g., copper and aluminum) provide conductive paths between the components on integrated circuits.
Copper is particularly advantageous for use in interconnect structures due to its desirable electrical properties. Copper interconnect system are typically fabricated using a damascene process in which trenches and vias are etched into dielectric layers. The trenches and vias are filled with copper which is then planarized using, for example, a chemical-mechanical planarization (CMP) process.
Copper interconnects are electrically isolated from each other by an insulating material. When the distance between adjacent metal interconnects and/or thickness of the insulating material has sub-micron dimensions, capacitive coupling may potentially occur between such interconnects. Capacitive coupling between adjacent metal interconnects may cause cross talk and/or resistance-capacitance (RC) delay which degrades the overall performance of the integrated circuit. In order to prevent capacitive coupling between adjacent metal interconnects, low dielectric constant (low k) insulating materials (e.g. dielectric constants less than about 4.0) are needed.
FIGS. 1A-1D illustrate an exemplary dual damascene structure formed by a “via-first” processing sequence. Referring first to FIG. 1A, a dielectric bulk insulating layer 110 and an underlying dielectric barrier layer 108 are stacked on another previously formed interconnect having a conductive layer 106 embedded in another dielectric bulk insulating layer 104 disposed on a substrate 102. An optional polish stop layer or anti-reflective coating (ARC) 112 may be disposed on the dielectric bulk insulating layer 110. The dielectric bulk insulating layer 110 is typically formed from a dielectric material having a dielectric constant lower than 4.0, such as FSG, polymer material, carbon containing silicon layer (SiOC), and the like.
A bottom anti-reflective coating (BARC) layer 114 is spin-applied to fill vias 128 formed by a via etching process and covers dielectric bulk insulating layer 110 before trench lithography. A photoresist layer 116 is disposed on the BARC layer 114 and patterned to define an opening 130 for forming trenches. A BARC etching process is performed to clear away a portion of the BARC layer 114 over the via opening 128 masked by the patterned photoresist layer 116 before etching the trenches, as shown in FIG. 1B. The BARC etching process is performed until the optional polish stop layer 112 defined by the photoresist layer 116 is exposed and the BARC layer 114 filling the via 128 is etched to a predetermined depth, as shown in FIG. 1B. Subsequently, a trench etching process is performed to etch the exposed polish stop layer 112 and the underlying dielectric bulk insulating layer 110 defined by the patterned photoresist layer 116, as shown in FIG. 1C. The trench etching process etches the dielectric bulk insulating layer 110 into a predetermined depth and defines trenches 122 in the dielectric bulk insulating layer 110. After the trench 122 has been formed, the remaining BARC layer 114 filling the via 128 and the photoresist layer 116 on the top surface of the dielectric bulk insulating layer 110 are removed from the substrate 102, thereby forming dual damascene structure on the substrate 102, as shown in FIG. 1D.
Typically, during the BARC 114 or photoresist layer 116 removal process, an oxygen containing plasma etch process is performed to react with the remaining BARC layer 114 and the photoresist layer 116 on the substrate 102, forming a carbon oxide polymer which is pumped out of the processing chamber. However, oxygen present plasma during the removal of BARC layer 114 and photoresist layer 116 may attack the exposed sidewall 120 and surface 126 of the trenches 122 and/or vias 128 formed in the dielectric bulk insulating layer 110. Oxygen may form a Si—O bond on the surface of the dielectric bulk insulating layer 110, which adversely affect the dielectric properties of the dielectric bulk insulating layer 110. For example, oxygen may accumulate on the sidewall 120 or exposed surface 126 of the low-k dielectric bulk insulating layer 110, and penetrate into the porous low-k dielectrics, thereby causing the carbon depletion at the film surface. Carbon depletion may cause the dielectric constant of the low-k material to undesirably increase, resulting in a “k loss” of the material dielectric properties. As a result, cross-talk and RC delay may increase after the BARC and photoresist etching process.
Furthermore, removal of the BARC and/or photoresist layer removal process may also leave contaminants 124, such as residual BARC, residual photoresist layer, impurities, organic or inorganic byproducts in the vias 128 and/or trenches 122. The contaminants 124 present in the vias 128 and/or trenches 122 may adversely effect the overall integration of the interconnection structure, resulting in poor device reliability and electrical performance.
Therefore, there is a need for an improved process for removing BARC in an interconnection structure.